When it comes to testing a design or a model, the surest way is to test it for real time conditions. But with increasing complexity of systems and ever greater progress being made in the computer realm, there is now a softer option of simulating the model and testing its feasibility before going in for the hardware. This event is to test your agility in simulation & programming. The packages available are MATLAB 7 with all tool boxes and Multisim 10 and MultiMCU 10.

Rules and Guidelines

1. The meet is open to B.Tech/B.E students of only EEE branch.
2. Maximum number of participants is two.
3. Topic will be given on the spot.
4. Time allowed for VIRTUOSE is 90 minutes.
5. Registration fees : Rs.100/- (Rs.75/- for IEEE members) per participant to be paid through DD in favor of the convener, JIJNASA-2008, BRECW , Hyderabad.
6. Registration by 07-03-2008 is necessary.
7. Registration form is available in our website.